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Netlist Receives Notices of Allowance for Additional HyperCloud Patents

02-Nov-2011 | Source : AG-IP News | Visits : 8026
IRVINE, Ca - Netlist Inc., a designer and manufacturer of high-performance memory subsystems, today announced in a press release that the US Patent and Trademark Office (USPTO) has recently issued notices of allowance to Netlist for three patent applications. 

These patents will provide the Company with enhanced intellectual property protection of its Rank Multiplication and Load Reduction technologies that represent key enabling innovations for HyperCloud™ products and the next generation cloud computing systems. The USPTO has issued these notices of allowance after taking into consideration more than 300 references and publications. 

Chief Executive Officer C.K. Hong said, "The Notices of Allowances for these newly allowed patent applications included explicit affirmations that the claims of these cases are patentable over the cited references and publications from the reexams currently being conducted for other Netlist patents. This set of allowances by the USPTO strengthens our growing intellectual property portfolio in a unique way and provides the ability to further protect these innovative technologies that are key to HyperCloud products." 

HyperCloud products provide economic and performance advantages that overcome inherent memory and speed limitations of existing multi-core CPU servers, addressing cloud scale server virtualization, high performance computing and big data analytics. 

The newly issued notices of allowances are for the following patent applications: 

US Patent Application No. 12/954,492 a continuation of U.S. Patent No. 7,864,627, entitled "Circuit for Providing Chip-Select Signals to a Plurality of Ranks of a DDR Memory Module,"
US Patent Application No. 13/032,470, a continuation of U.S. Patent No. 7,916,574, entitled "Circuit for Memory Module,"
US Patent Application No.12/981,380, a continuation of U.S. Patent No. 7,881,150, entitled "Circuit Providing Load Isolation and Memory Domain Translation for Memory Module."
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